august 2014 FCD1300N80Z ? n-channel superfet ? ii mosfet ?2014 fairchild semiconductor corporation FCD1300N80Z rev. c0 www.fairchildsemi.com 1 FCD1300N80Z n-channel superfet ? ii mosfet 800 v, 4 a, 1.3 ? features ?r ds(on) = 1.05 ??? typ.) ? ultra low gate charge (typ. q g = 16.2 nc) ?low e oss (typ. 1.57 uj @ 400v) ? low effective output capacitance (typ. c oss(eff.) = 48.7 pf) ? 100% avalanche tested ?rohs compliant ? esd improved capability applications ? ac - dc power supply ? led lighting description superfet ? ii mosfet is fairchil d semiconductor?s brand-new high voltage super-junction (sj) mosf et family that is utilizing charge balance technology for outstanding low on-resistance and lower gate charge performance. this technology is tailored to minimize conduction loss , provide superior switching performance, dv/dt rate and higher avalanche energy. in addition, internal gate-source esd diode allows to withstand over 2kv hbm surge stress.consequently, superfet ii mosfet is very suitable for t he switching power applications such as audio, laptop adapter, lighting, atx power and industrial power applications. ? absolute maximum ratings t c = 25 o c unless otherwise noted. thermal characteristics symbol parameter FCD1300N80Z unit v dss drain to source voltage 800 v v gss gate to source voltage - dc 20 v - ac (f > 1 hz) 30 i d drain current - continuous (t c = 25 o c) 4 a - continuous (t c = 100 o c) 2.5 i dm drain current - pulsed (note 1) 12 a e as single pulsed avalanche energy (note 2) 48 mj i ar avalanche current (note 1) 0.8 a e ar repetitive avalanche energy (note 1) 0.26 mj dv/dt mosfet dv/dt 100 v/ns peak diode recovery dv/dt (note 3) 20 p d power dissipation (t c = 25 o c) 52 w - derate above 25 o c0.42w/ o c t j , t stg operating and storage temperature range -55 to +150 o c t l maximum lead temperature for soldering, 1/8? from case for 5 seconds 300 o c symbol parameter FCD1300N80Z unit r ? jc thermal resistance, junction to case, max. 2.4 o c/w r ? ja thermal resistance, junction to ambient, max. 100 d-pak g s d g d s
FCD1300N80Z ? n-channel superfet ? ii mosfet ?2014 fairchild semiconductor corporation FCD1300N80Z rev. c0 www.fairchildsemi.com 2 package marking and ordering information electrical characteristics t c = 25 o c unless otherwise noted. off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics part number top mark package packing method reel size tape width quantity FCD1300N80Z fcd130080z dpak tape and reel 330 mm 16 mm 2500 units symbol parameter test conditions min. typ. max. unit bv dss drain to source breakdown voltage v gs = 0 v, i d = 1 ma, t j = 25 ? c 800 - - v ? bv dss / ? t j breakdown voltage temperature coefficient i d = 1 ma, referenced to 25 o c - 0.85 - v/ o c i dss zero gate voltage drain current v ds = 800 v, v gs = 0 v - - 25 ? a v ds = 640 v, v gs = 0 v, t c = 125 o c- - 250 i gss gate to body leakage current v gs = 20 v, v ds = 0 v - - 10 ? a v gs(th) gate threshold voltage v gs = v ds , i d = 0.4 ma 2.5 - 4.5 v r ds(on) static drain to source on resistance v gs = 10 v, i d = 2 a - 1.05 1.3 ? g fs forward transconductance v ds = 20 v, i d = 2 a -4.5- s c iss input capacitance v ds = 100 v, v gs = 0 v, f = 1 mhz - 661 880 pf c oss output capacitance - 22.3 30 pf c rss reverse transfer capacitance - 0.74 - pf c oss output capacitance v ds = 480 v, v gs = 0 v, f = 1 mhz - 11.4 - pf c oss(eff.) effective output capacitance v ds = 0 v to 480 v, v gs = 0 v - 48.7 - pf q g(tot) total gate charge at 10v v ds = 640 v, i d = 4 a, v gs = 10 v (note 4) - 16.2 21 nc q gs gate to source gate charge - 3.5 - nc q gd gate to drain ?miller? charge - 6.8 - nc esr equivalent series resistance f = 1 mhz - 4 - ? t d(on) turn-on delay time v dd = 400 v, i d = 4 a, v gs = 10 v, r g = 4.7 ? (note 4) -1438ns t r turn-on rise time - 8.3 27 ns t d(off) turn-off delay time - 33 76 ns t f turn-off fall time - 6 22 ns i s maximum continuous drain to source diode forward current - - 4 a i sm maximum pulsed drain to source diode forward current - - 12 a v sd drain to source diode forward voltage v gs = 0 v, i sd = 4 a - - 1.2 v t rr reverse recovery time v gs = 0 v, i sd = 4 a, di f /dt = 100 a/ ? s -275- ns q rr reverse recovery charge - 2.9 - ? c notes: 1. repetitive rating: pulse width limit ed by maximum junction temperature. 2. i as = 0.8 a, r g = 25 ? , starting t j = 25 ? c 3. i sd ? 4 a, di/dt ? 200 a/ ? s, v dd ? bv dss , starting t j = 25 ? c 4. essentially independent of operating temperature typical characteristic.
FCD1300N80Z ? n-channel superfet ? ii mosfet ?2014 fairchild semiconductor corporation FCD1300N80Z rev. c0 www.fairchildsemi.com 3 typical performance characteristics figure 1. on-region characteristics figure 2. transfer characteristics 0.5 1 10 20 0.3 1 10 20 *notes: 1. 250 p s pulse test 2. t c = 25 o c i d , drain current[a] v ds , drain-source voltage[v] v gs = 20.0v 10.0v 8.0v 7.0v 6.5v 6.0v 5.5v 5.0v 34567 0.1 1 10 20 -55 o c 150 o c *notes: 1. v ds = 20v 2. 250 p s pulse test 25 o c i d , drain current[a] v gs , gate-source voltage[v] figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate vo l tage variation vs. source current and temperature 0 . 00 . 40 . 81 . 2 0.001 0.01 0.1 1 10 20 *notes: 1. v gs = 0v 2. 250 p s pulse test 150 o c i s , reverse drain current [a] v sd , body diode forward voltage [v] 25 o c 024681012 0.5 1.0 1.5 2.0 2.5 *note: t c = 25 o c v gs = 20v v gs = 10v r ds(on) [ : ], drain-source on-resistance i d , drain current [a] figure 5. capacitance characteristics figure 6. gate charge characteristics 0.1 1 10 100 1000 0.1 1 10 100 1000 10000 30000 c oss c iss c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd *note: 1. v gs = 0v 2. f = 1mhz c rss capacitances [pf] v ds , drain-source voltage [v] 061 21 8 0 2 4 6 8 10 *note: i d = 4a v ds = 160v v ds = 400v v ds = 640v v gs , gate-source voltage [v] q g , total gate charge [nc]
FCD1300N80Z ? n-channel superfet ? ii mosfet ?2014 fairchild semiconductor corporation FCD1300N80Z rev. c0 www.fairchildsemi.com 4 typical performance characteristics (continued) figure 7. breakdown voltage variation figure 8. on-resistance variation vs. temperature vs. temperature -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 *notes: 1. v gs = 10v 2. i d = 2a r ds(on) , [normalized] drain-source on-resistance t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 *notes: 1. v gs = 0v 2. i d = 1ma bv dss , [normalized] drain-source breakdown voltage t j , junction temperature [ o c] figure 9. maximum safe operating area figure 10. maximum drain current 0.1 1 10 100 1000 0.01 0.1 1 10 30 10 p s 100 p s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse dc 25 50 75 100 125 150 0 1 2 3 4 5 i d , drain current [a] t c , case temperature [ o c] vs. case temperature figure 11. eoss vs. drain to source voltage 0 200 400 600 800 0 1 2 3 4 5 e oss , [ p j] v ds , drain to source voltage [v]
FCD1300N80Z ? n-channel superfet ? ii mosfet ?2014 fairchild semiconductor corporation FCD1300N80Z rev. c0 www.fairchildsemi.com 5 typical performance characteristics (continued) figure 12. transient thermal response curve 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 0.1 1 single pulse *notes: 1. z t jc (t) = 2.4 o c/w max. 2. duty factor, d= t 1 /t 2 3. t jm - t c = p dm * z t jc (t) rectangular pulse duration [sec] z t jc (t), thermal response [ o c/w ] 0.01 0.1 0.2 0.05 0.02 0.5 t 1 p dm t 2 4 0.005
FCD1300N80Z ? n-channel superfet ? ii mosfet ?2014 fairchild semiconductor corporation FCD1300N80Z rev. c0 www.fairchildsemi.com 6 figure 13. gate charge test circuit & waveform figure 14. resistive switch ing test circuit & waveforms figure 15. unclamped inductive switching test circuit & waveforms v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v gs i g = const.
FCD1300N80Z ? n-channel superfet ? ii mosfet ?2014 fairchild semiconductor corporation FCD1300N80Z rev. c0 www.fairchildsemi.com 7 figure 16. peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
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